# Context pack: AMD

> You are a structural analyst. The material below is from PlexusGraph — a knowledge-graph research publication. Reason with the user grounded in it: surface the structure, the feedback loops, the chokepoints and flywheels, and the non-obvious connections. When you make a claim from it, you can point to the sources.

**In one line:** AMD: The Really Good Racecar That Keeps Losing Because the Track Was Built for Someone Else

Source: https://plexusgraph.dev/companies/amd

## Brief

*Based on 135 related nodes across 10 research explorations in the semiconductors sector.*

AMD makes some of the best chips in the world. Their latest AI processors are objectively better than their main competitor's on several key measures. And yet AMD keeps losing. Understanding why tells you almost everything important about how the AI chip industry actually works — and why being technically superior is not the same as winning.

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## The Sport AMD Is Playing In

Imagine the AI chip industry as a professional racing league. NVIDIA built the track, wrote the rules, and trained all the mechanics. Their cars are good — not always the fastest on paper — but every pit crew in the world knows how to work on them. AMD shows up with a faster car. Wider. More fuel capacity. Better on long straight stretches. But here's the problem: the pit crews only know NVIDIA's car. The trackside software only talks to NVIDIA's telemetry system. The training schools only teach NVIDIA mechanics. AMD's car sits in the paddock looking impressive while NVIDIA's cars keep winning races.

That is the AMD situation in AI chips, in 2026, more or less exactly.

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## What AMD Actually Does Well

### Their Memory Advantage Is Real

The most concrete thing AMD has going for it is memory — specifically, how much memory their AI chips carry and how fast they can move data in and out of it.

Here is why this matters. Modern AI models, especially when they are generating text or answering questions (rather than being trained from scratch), spend most of their time shuffling enormous tables of numbers called a "KV cache" back and forth through memory. The bigger the context window — meaning the more of a conversation the AI can "remember" at once — the bigger this table gets, and the more memory bandwidth you need to handle it.

AMD's MI300X chip carries 192 gigabytes of high-bandwidth memory, moving data at 5.3 terabytes per second. NVIDIA's H100, which was the gold standard until recently, carries 80 gigabytes at 3.35 terabytes per second. AMD has more than twice the memory at a meaningfully faster speed. For the specific job of running AI inference — serving answers to users — this is a genuine, measurable advantage.

The non-obvious part: this advantage is not static. It is *growing in importance* because context windows keep getting longer. The longer the context window, the more AMD's memory lead matters. AMD's roadmap also shows this advantage continuing into future generations (the MI350X and MI400), so it is not a one-time lucky spec win.

### The Inference Market Is AMD's Territory

AI work splits into two phases: **training** (teaching the model from scratch, which takes months and enormous compute) and **inference** (actually using the trained model to answer questions, which happens billions of times a day). These two phases have very different hardware requirements.

Training is locked up. NVIDIA built a software ecosystem called CUDA over 19 years that makes their chips by far the easiest to use for training. All the best training software, all the optimized algorithms, all the researcher habits — they are written for NVIDIA. This is not changing anytime soon.

But inference is different. Inference workloads do not need CUDA's specialized training toolkit nearly as much. They need memory bandwidth and memory capacity — which is exactly where AMD excels. The inference market is genuinely more open to alternatives. This is the only realistic competitive space AMD has against NVIDIA, and it is a large and growing one as AI gets deployed at scale.

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## Why AMD Keeps Not Winning Despite Good Hardware

### The Software Gap Is the Real Problem

AMD's hardware advantage has a very clear enemy: software friction. Developers who want to use AMD chips instead of NVIDIA chips have to rewrite or port significant amounts of their code. NVIDIA's CUDA ecosystem — their programming tools, their libraries, their optimizations — took nearly two decades to build. AMD's equivalent (called ROCm) is improving but is not there yet.

The result is a paradox that the research data captures directly: AMD's MI300X is objectively superior on inference hardware specs, and yet it is not taking over the inference market. The reason is that moving from NVIDIA to AMD requires engineering effort that most teams cannot justify unless the cost savings are overwhelming. Software friction is invisible on a spec sheet but very visible when your engineering team has to spend six months porting code.

Intel's Gaudi3 chip is a cautionary example. It also had competitive hardware specs for AI inference. It also lacked software ecosystem depth. It is now effectively dead in the market. The research data explicitly flags this as a warning for AMD — hardware is necessary but not sufficient.

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## The Supply Chain AMD Does Not Control

Here is something that does not show up in chip spec comparisons: AMD does not make its own chips. Neither does NVIDIA. Both companies design chips and then pay TSMC in Taiwan to manufacture them.

This creates a structural vulnerability that affects AMD regardless of how good its engineers are. There is essentially one company in the world that can manufacture leading-edge AI chips at scale: TSMC. And there is essentially one place in the world where the most critical step in that process — advanced chip packaging, called CoWoS — is done: Taiwan. AMD has no backup plan for this. Neither does NVIDIA. But it means AMD's fate is partially in the hands of a geopolitical situation it cannot influence.

Additionally, the high-bandwidth memory that makes AMD's chips good comes primarily from one company in South Korea (SK Hynix, which controls about 62% of this specialized memory market). AMD's memory advantage depends on a supply chain that is geographically concentrated and subject to government restrictions. Export controls on this type of memory have already been imposed and could tighten further.

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## The China Question

Export controls — government restrictions on selling advanced chips to China — have created an unusual commercial opportunity for AMD. Under current US policy, AMD can sell a slightly downgraded version of its AI chip (called the MI308) to Chinese customers, paying 15% of that revenue to the US Treasury as a kind of trade tax. NVIDIA's China-market chip was under tighter restrictions for longer.

This gives AMD a revenue stream in a market that is hungry for AI compute and short on alternatives. Huawei makes competing chips inside China, but AMD's MI308 still appears to be a viable option for Chinese AI companies. Whether this revenue is material or modest depends on factors not fully captured in the available research, but the access itself is a comparative advantage over the period when NVIDIA's equivalent was restricted.

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## The Clock Is Ticking

AMD has a time window that matters. NVIDIA's next-generation architecture, called Vera Rubin, is expected in the second half of 2026. It will carry 288 gigabytes of next-generation memory at 22 terabytes per second — directly targeting the memory bandwidth gap that AMD has been exploiting.

Once Vera Rubin ships at volume, AMD's current memory advantage narrows or closes at the top of the market. This gives AMD roughly 12 to 18 months to do something with its current lead: sign up customers, build reference deployments, develop software integrations, create switching costs. If AMD can get enough inference workloads running on its hardware during this window, those customers will face their own switching costs to move away — just as NVIDIA's customers face switching costs moving away from CUDA. Installed base creates inertia in both directions.

The window is real but the clock is running.

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## The Longer-Term Pressure AMD Did Not Create

There is a force in the background that could eventually shrink AMD's market opportunity regardless of what AMD does: the big cloud companies building their own chips.

Google, Amazon, Meta, and Microsoft are all investing heavily in custom-designed silicon — chips built specifically for their own AI workloads. These are not general-purpose AI chips you can buy. They are internal tools, designed to squeeze maximum efficiency from the specific models and workloads these companies run. As this trend accelerates, the pool of hyperscaler customers buying chips from AMD (or NVIDIA) instead of making their own shrinks.

This is a slow-moving structural pressure, not an immediate crisis. The custom chip programs are expensive, take years to mature, and are most effective for stable, high-volume workloads. But it means AMD's long-term ceiling in the hyperscaler inference market is lower than it might appear today.

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## One Non-Obvious Finding Worth Noting

The rise of efficient AI architectures — models designed to do more with less compute, like the DeepSeek family — turns out to be structurally good for AMD in a specific way. These models are particularly sensitive to memory bandwidth and memory capacity, not raw compute power. They amplify AMD's hardware advantages rather than neutralizing them.

This is counterintuitive. You might expect that "better, cheaper AI" helps NVIDIA because NVIDIA has more market share to benefit from a rising tide. But the specific shape of efficient-architecture workloads happens to favor AMD's hardware profile. The research data captures this directly, calling it the "DeepSeek-AMD Memory Resonance Effect." Whether AMD converts this structural alignment into actual customer wins is a separate question — but the underlying alignment is real.

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## Bottom Line

AMD is a company with genuine hardware advantages trapped in a market that was built by and for its main competitor. The chips are good. On the specific task of running AI inference workloads — serving AI answers to users at scale — AMD's memory specifications are competitive or superior. The company has a real product, a real roadmap, and a real commercial opening.

The central problem is that technical merit has never been sufficient in this market. NVIDIA's competitive advantage is not just good hardware; it is nearly two decades of software infrastructure that makes switching expensive. AMD's highest-leverage action is investing in closing the software gap (ROCm, their programming toolkit), because that is the only path to converting hardware quality into market share. Everything else — better chips, lower prices, memory bandwidth leads — has been tried and found insufficient without the software layer.

The next 18 months matter more than usual. AMD has a window of hardware advantage before NVIDIA's next generation closes it. The question is whether AMD can use that window to build the kind of installed base and software depth that creates its own switching costs. If it does, it becomes a durable #2 in AI inference. If it does not, it remains a very capable company perpetually described in terms of what it almost achieved.

## Deep analysis

*135 related nodes, 911 connections across 10 explorations in the semiconductors sector.*

# AMD — Company Brief
**Sector:** Semiconductors | **Data basis:** 135 nodes, 911 connections across 10 research explorations | **Date:** April 2026

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## Structural Position

AMD occupies a structurally secondary position in the AI compute stack — significant enough to appear in every major sub-graph of the research corpus, but consistently defined by its relationship to NVIDIA's dominance rather than as an independent competitive pole. The single most revealing signal in the graph is the connection asymmetry: **NVIDIA GPU Monopoly Economics** holds 43 connections to AMD — the largest of any node — followed by **Nvidia CUDA Ecosystem Lock-in** at 20. AMD is more legible as a response function to NVIDIA than as an independent strategic actor.

Within industry structure, AMD sits at the intersection of three structural forces:

1. **The Fabless Cliff** (w=8.5, 10 connections to AMD): AMD manufactures nothing. Like NVIDIA, it is entirely dependent on **TSMC Geopolitical Chokepoint** (17 connections to AMD) and **CoWoS Advanced Packaging Chokepoint** (12 connections to AMD) for physical production. The graph edge `Fabless Cliff --[depends_on]--> TSMC Geopolitical Chokepoint (w=9.5)` applies directly to AMD.

2. **Training vs Inference Hardware Bifurcation** (15 connections to AMD): AMD's strategic territory is structurally constrained to the inference zone. The **CUDA Fortress vs Inference Open Market Topology** node (w=9) synthesizes this bifurcation and its implications — AMD cannot contest training (CUDA Fortress) but has a legitimate position in inference (Open Market).

3. **AMD Hardware Superiority Paradox** (w=7.8): The central paradox of AMD's position is that its MI300X has objectively superior hardware specs on the inference-critical metric (memory bandwidth) yet cannot convert this into market share. This node explicitly demonstrates NVIDIA's CUDA ecosystem lock-in (`AMD Hardware Superiority Paradox --[demonstrates]--> Nvidia CUDA Ecosystem Lock-in, w=9.5`).

The graph structure reveals AMD as a company with genuine hardware-layer advantages that are systematically frustrated by software-layer lock-in it does not control.

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## Key Strengths

### Durable Advantages

**1. Memory Bandwidth Lead — Structurally Timed to Market Shift (w=7.5–8.5)**
The **AMD MI300X Memory-Moat Inference Strategy** (w=7.5, 11 connections) is the graph's most concrete AMD-specific node. MI300X: 192GB HBM3 at 5.3 TB/s vs H100's 80GB at 3.35 TB/s. This advantage compounds with two powerful amplifiers in the graph:
- `KV Cache Memory Wall --[amplifies]--> AMD MI300X Memory-Moat Inference Strategy (w=9)` — as context windows grow, KV cache memory pressure intensifies, making AMD's memory density advantage progressively more valuable.
- `DeepSeek-AMD Memory Resonance Effect --[amplifies]--> AMD MI300X Memory-Moat Inference Strategy (w=8)` — DeepSeek-style efficient architectures are disproportionately memory-bandwidth-bound, amplifying AMD's structural edge in the inference workloads these models generate.

The **AMD MI350X Chiplet Memory Supremacy** node (w=8 connections) supersedes MI300X (`AMD MI350X Chiplet Memory Supremacy --[supersedes]--> AMD MI300X Memory-Moat Inference Strategy, w=8.5`), and **AMD MI400 CDNA5 HBM4 Architecture** addresses the KV Cache Memory Wall (`AMD MI400 CDNA5 HBM4 Architecture --[addresses]--> KV Cache Memory Wall, w=8.5`). AMD's hardware roadmap is directionally aligned with the market's structural shift toward inference.

**2. Inference Market Structural Opening**
The **CUDA Fortress vs Inference Open Market Topology** (w=9) explicitly identifies the inference market as structurally open: training requires CUDA custom kernels and NVLink-class communication; inference does not. AMD's hardware moat is specifically located in the zone where NVIDIA's software moat is weakest. This is not coincidental positioning — it is the only viable competitive vector given CUDA's durability in training.

**3. Export Control Commercial Positioning**
Under **Trump Commerce-for-Revenue Chip Policy** (w=8.5), AMD pays 15% of MI308 revenue from China sales to the US Treasury, but retains China market access. The edge `Trump Commerce-for-Revenue Chip Policy --[narrows]--> China AI Compute Demand-Supply Chasm (w=8)` indicates AMD benefits from reduced constraint pressure relative to the Biden-era lockout. This creates a revenue stream that competitors without approved downgraded SKUs cannot access.

**4. ROCm Insurgency Potential**
**AMD ROCm Open Hardware Insurgency** constrains NVIDIA's hardware lock-in via open-source strategy (`AMD ROCm Open Hardware Insurgency --[constrains]--> NVIDIA Hardware Lock-In via Open-Source Strategy, w=7.5`). The **AMD HIP 7.0 CUDA Semantic Convergence Strategy** enables MI300X adoption and targets the MoE inference workload market (`AMD HIP 7.0 CUDA Semantic Convergence Strategy --[enables]--> AMD MI300X Memory-Moat Inference Strategy, w=8.5`). These are not yet decisive but represent a structural counter-pressure.

### Fragile Advantages

The memory bandwidth lead is hardware-replicable. NVIDIA's **Vera Rubin Architecture (2026)** (w=8) deploys 288GB HBM4 per GPU at 22 TB/s — directly targeting AMD's memory moat. The edge `NVIDIA Vera Rubin Architecture --[competes_with]--> AMD MI400 CDNA5 HBM4 Architecture (w=9)` confirms head-on competition. AMD's advantage is a moving target, not a structural moat.

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## Structural Vulnerabilities

### Immediate

**1. ROCm Software Ecosystem Gap (10 connections to AMD)**
The graph's most consequential AMD vulnerability. **AMD ROCm Software Ecosystem Gap** constrains the MI300X Memory-Moat Inference Strategy directly (`AMD ROCm Software Ecosystem Gap --[constrains]--> AMD MI300X Memory-Moat Inference Strategy, w=8`). The **AMD Hardware Superiority Paradox** node (w=7.8) demonstrates that superior hardware specs do not convert to market share when software friction is high — a pattern the graph explicitly generalizes from Intel Gaudi3's collapse: `Intel Gaudi3 Software Ecosystem Collapse --[warns]--> AMD Hardware Superiority Paradox (w=8.5)`. The CUDA fortress is proven durable specifically by Intel's failure to breach it with competitive hardware.

**2. CoWoS Packaging Dependency (12 connections to AMD)**
Every AMD MI-series chip requires TSMC's CoWoS advanced packaging. The **CoWoS Advanced Packaging Chokepoint** (w=8.5) is described as "more constraining than chip design or fab capacity." AMD has no control over this bottleneck and no alternative supplier. Capacity is sold out through 2026, and TSMC's CoWoS lines are almost entirely in Taiwan.

**3. HBM Supply Chain Exposure (11 connections to AMD)**
AMD's memory advantage depends on HBM supply. **HBM Export Control Chokepoint** (w=8.5) imposes constraints on HBM flows, particularly in relation to China. **HBM Memory Korea Concentration** (w=8) — SK Hynix 62%+ of global HBM — creates a single-supplier dependency. AMD's memory moat is structurally dependent on a supply chain it does not control and that is subject to geopolitical intervention.

### Long-Term

**4. Hyperscaler Custom Silicon (XPU) Strategy (14 connections to AMD)**
The graph identifies this as undermining NVIDIA GPU Monopoly Economics (`Hyperscaler Custom Silicon (XPU) Strategy --[undermines]--> NVIDIA GPU Monopoly Economics, w=8.5`). The same pressure applies to AMD: if Google (Ironwood TPU), Microsoft (Maia), Meta (MTIA), and Amazon (Trainium/Inferentia) build their own accelerators at scale, AMD's total addressable market in hyperscaler inference shrinks regardless of its hardware advantages.

**5. TSMC Geopolitical Risk (17 connections to AMD)**
**Taiwan Contingency AI Power Collapse** (11 connections to AMD) represents existential supply chain risk. AMD is entirely dependent on TSMC — Fab 21 Arizona production is partially mitigating this (`TSMC Arizona GigaFab Program --[constrains]--> Taiwan Contingency AI Power Collapse, w=6`) but coverage is limited and packaging capacity remains Taiwan-concentrated.

**6. MoE Architecture Fit Constraints**
**MoE Sparse Activation Hardware Fit Matrix** (w=8) constrains AMD's MI300X Memory-Moat Inference Strategy (`MoE Sparse Activation Hardware Fit Matrix --[constrains]--> AMD MI300X Memory-Moat Inference Strategy, w=7.5`). MoE models are memory-bandwidth-bound but not in the simple way AMD's memory moat addresses — expert routing creates irregular memory access patterns that favor architectures with high on-chip SRAM (Cerebras, Google TPU) rather than large off-chip HBM.

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## Competitive Dynamics

### AMD vs NVIDIA

The graph encodes a structural ceiling on AMD's competition with NVIDIA. The **CUDA 19-Year Software Moat** (w=8.2) controls the AI compute stack in training, and **AMD Hardware Superiority Paradox** demonstrates that hardware specs alone cannot breach it. The training market is described as a "Fortress" in the **CUDA Fortress vs Inference Open Market Topology** node — CUDA Fortress vs Inference Open Market Topology `--[explains_durability_of]--> Nvidia CUDA Ecosystem Lock-in (w=9)`.

AMD's realistic competitive surface with NVIDIA is the inference market, where the software moat is weaker and AMD's memory bandwidth creates genuine cost advantages for memory-bandwidth-bound workloads. The graph does not contain a node suggesting AMD has a path to training market penetration.

NVIDIA's response is the **Vera Rubin Architecture (2026)** directly targeting AMD's memory advantage, and the **NVIDIA NVLink Fusion Ecosystem Judo Strategy** — absorbing third-party chips (potentially AMD) into NVLink scale-up infrastructure, turning potential competition into dependency.

### AMD vs Intel

Intel's dysfunction is structurally neutral to positive for AMD. **Intel Foundry Services Crisis** (w=7.5) and **Intel Gaudi3 Software Ecosystem Collapse** validate AMD's position as the credible #2 in both CPUs and AI accelerators. The **IDM 2.0 Competitor Trust Paradox** means AMD would not tape out advanced products on Intel Foundry — AMD routes to TSMC, benefiting from Intel Foundry's customer acquisition failures.

Intel Gaudi3's collapse is explicitly cited as a warning for AMD (`Intel Gaudi3 Software Ecosystem Collapse --[warns]--> AMD Hardware Superiority Paradox, w=8.5`), but it also removes a competitor from the inference hardware market.

### AMD vs Custom Silicon (ASICs)

**Custom Silicon ASIC Economics** (9 connections to AMD) has an interesting relationship to AMD: `AMD Hardware Superiority Paradox --[contradicts]--> Custom Silicon ASIC Economics (w=7.5)`. If AMD's hardware advantages over NVIDIA are real but software-frustrated, ASICs face the same software friction problem but with even less ecosystem support. However, hyperscaler ASICs (Google TPU, AWS Trainium) are built for internal workflows where software integration is under the hyperscaler's control — this constraint does not apply to them the same way.

### AMD vs Qualcomm

**Qualcomm AI200/AI250 Datacenter Inference Entry** competes directly with AMD's MI300X Memory-Moat Inference Strategy (`Qualcomm AI200/AI250 --[competes_with]--> AMD MI300X Memory-Moat Inference Strategy, w=8`). Qualcomm's datacenter inference push represents a new entrant in AMD's specific competitive zone — not a legacy competitor like Intel but a hardware-first company with its own competitive software ecosystem (QNN/SNPE).

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## Regulatory Exposure

AMD faces a dual regulatory exposure:

**Export Control Architecture**
The **US BIS Export Control Ratchet** (9 connections to AMD) affects AMD through two channels: (1) direct controls on AMD chip exports to China, and (2) HBM export controls that constrain AMD's own supply chain. AMD responded by developing the MI308 — a downgraded SKU engineered to fall below BIS performance thresholds — enabling continued China market access under the Trump Commerce-for-Revenue framework at a 15% revenue tax.

The **HBM Export Control Chokepoint** (w=8.5, 11 connections to AMD) constrains AMD's supply chain: BIS banned HBM exports to China (`US BIS Export Control Ratchet --[triggers]--> HBM Export Control Chokepoint, w=9`), and extended controls to South Korean HBM suppliers. AMD sources HBM from SK Hynix, Micron, and Samsung — all subject to these controls in their China business, creating indirect supply complexity.

**Comparative Position**
AMD's regulatory position is marginally more favorable than NVIDIA's: the MI308 China SKU approval suggests AMD maintained regulatory access while NVIDIA's H20 faced extended restrictions. However, **DeepSeek Compute Efficiency Paradox** undermines HBM export controls' strategic logic (`DeepSeek Compute Efficiency Paradox --[undermines]--> HBM Export Control Chokepoint, w=7.5`), which creates uncertainty about future control regimes — if algorithmic efficiency partially substitutes for hardware, controls may tighten or shift scope in ways that affect AMD's downgraded SKU strategy.

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## Strategic Leverage Points

The graph identifies several high-leverage intervention points where AMD could address multiple constraints simultaneously:

**1. ROCm Ecosystem Investment (highest multiplier)**
The AMD ROCm Software Ecosystem Gap constrains the MI300X Memory-Moat Inference Strategy (w=8) and is the primary reason the AMD Hardware Superiority Paradox persists. The **AMD HIP 7.0 CUDA Semantic Convergence Strategy** is the stated mechanism for closing this gap. This is AMD's highest-leverage action because it is (a) within AMD's control, (b) addresses the primary conversion failure between hardware advantage and market share, and (c) targets the inference market where CUDA's moat is structurally weakest. The graph edge `ROCm Path Dependency Trap --[explains_mechanism_of]--> AMD Hardware Superiority Paradox (w=9)` confirms this is the mechanism, not a symptom.

**2. Inference Market Entrenchment Before Vera Rubin**
AMD has a time-bounded window before NVIDIA's Vera Rubin architecture (H2 2026) closes the memory bandwidth gap. `NVIDIA Vera Rubin Architecture --[competes_with]--> AMD MI400 CDNA5 HBM4 Architecture (w=9)` indicates direct competition at the next generation. AMD's strategic window to establish inference market share, customer integrations, and software ecosystem depth is the 12–18 months before Vera Rubin achieves volume production. Installed base at inference scale creates switching costs that partially mirror CUDA's training moat.

**3. DeepSeek Efficiency Doctrine Alignment**
**DeepSeek Efficiency Doctrine** (11 connections to AMD) and **DeepSeek-AMD Memory Resonance Effect** represent a structural alignment between AMD's hardware profile and the dominant inference workload pattern. DeepSeek-style models are memory-bandwidth-bound and memory-capacity-constrained — precisely where AMD's MI300X/MI350X excels. AMD's leverage point is making this alignment legible and proven through reference deployments, converting an alignment in graph structure into customer adoption evidence.

**4. Chiplet Architecture Diversification**
**Chiplet Disaggregation Resilience Strategy** depends on CoWoS Advanced Packaging — but chiplet architectures also create potential for multi-source assembly that could reduce single-supplier packaging risk. AMD's existing chiplet expertise (Infinity Fabric, used in Epyc and Radeon) positions it to develop packaging alternatives that could partially mitigate CoWoS concentration. This is a long-term leverage point, not near-term.

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## Open Questions

**1. ROCm Trajectory Ambiguity**
The graph identifies the ROCm Software Ecosystem Gap as AMD's primary constraint but does not quantify its rate of closure. AMD HIP 7.0's CUDA Semantic Convergence Strategy is named but its adoption curve, enterprise integration status, and performance gap vs CUDA on common workloads (FlashAttention, NCCL equivalents) are not captured in the available data. Whether ROCm is narrowing the gap meaningfully or merely improving incrementally is the most consequential unknown for AMD's AI hardware prospects.

**2. Hyperscaler Inference Allocation Decisions**
**Hyperscaler Custom Silicon (XPU) Strategy** (14 connections to AMD) is described as undermining NVIDIA's monopoly, but the data does not specify what share of inference workloads hyperscalers direct to AMD vs their own ASICs vs NVIDIA. The inference "open market" may be more open in theory than in practice if hyperscalers increasingly vertically integrate inference hardware at scale.

**3. AMD's Training Market Ceiling**
The graph treats AMD's training market exclusion as near-total given CUDA Fortress dynamics. However, it does not address whether AMD has any training customers at scale (e.g., cloud providers or researchers using ROCm-compatible frameworks) or what volume threshold would justify AMD investing in training-grade interconnect (NVLink analog). The training floor for AMD is uncharacterized.

**4. MI308 China Revenue Contribution**
AMD's China market access under the Trump Commerce-for-Revenue framework (MI308 at 15% revenue tax) is noted, but the actual or projected revenue contribution from this channel is absent from the graph data. Given China AI Compute Demand-Supply Chasm dynamics, this could be material or negligible depending on MI308 performance relative to Huawei Ascend alternatives.

**5. Packaging Alternatives**
CoWoS is identified as a critical constraint, but whether AMD has engaged with Intel Foundry's advanced packaging capabilities (EMIB, Foveros) or other packaging providers as strategic alternatives is not captured. The TSMC-Intel Foundry Joint Venture (w=9) could theoretically open packaging alternatives for AMD, but the data does not explore this path.

**6. AMD CPU/GPU Integrated Stack**
AMD's dual CPU (Epyc) and GPU (Instinct) portfolio creates potential for integrated compute stack offerings (CPU+accelerator on same substrate) that NVIDIA cannot replicate. The graph does not explore whether this integration path is being pursued or whether it constitutes a competitive differentiator in inference deployments.

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*This brief synthesizes graph-structured research data. All claims are grounded in node content, edge labels, and edge weights as documented. Node weights reflect the research corpus's assessed importance (0–10 scale). This document does not constitute investment advice.*